Hackaday · Creativity & design

Emulating Memory Access: How Hard Can It Be?

Emulating memory access accurately, especially across different CPU architectures like x86 and ARM, presents significant challenges beyond simple instruction translation.

The core issue lies in how CPUs ensure that memory writes by one processor are visible to others. x86 employs a Total Store Ordering (TSO) model, guaranteeing strong visibility, while ARM uses a weaker model for performance, allowing more reordering.

Emulators can attempt to bridge this gap by translating x86 memory operations to ARM's acquire/release operations, but this can be performance-intensive. Newer ARM extensions and Apple Silicon's TSO mode offer improvements.

Unaligned memory accesses and atomic operations, common in x86 software, are problematic on ARM. Emulators may need to intercept alignment faults and insert code barriers, with split-lock operations potentially causing extreme slowdowns.

Specific hardware improvements, like Qualcomm's coherent cache-line atomics and Linux kernel optimizations, address some of these atomic operation issues.

Write-combined GPU memory presents another hurdle. PC games often rely on x86 ordering semantics for uncached buffers, and ARM's lack of direct equivalents can lead to drastic performance degradation, with bandwidth reductions over 800x observed.

In Unified Memory Architecture (UMA) systems, drivers can sometimes mitigate these issues by using ordinary cache-coherent memory.

Ultimately, modern emulators often need to replicate complex architectural assumptions that software depends on, rather than just translating instructions, to achieve accurate behavior.

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